The present invention relates to phase detector for use in a phase-locked loop, for instance.
The phase detector is applied, for example, to a phase-locked loop as shown in FIG. 1. As is well-known in the art, the phase-locked loop comprises, for instance, a phase detector 1, a low-pass filter 2, a voltage-controlled oscillator 3, and a 1/N frequency divider 4.
The phase detector 1 receives a signal of a reference frequency fr, compares the phase of the input signal fr and the phase of a signal fv from the 1/N frequency divider 4, and applies the phase detected output K.sub.PD to the voltage-controlled oscillator 3 via the low-pass filter 2. The oscillation frequency fout of the voltage-controlled oscillator 3 is controlled so that the two input signals fr and fv to the phase detector 1 may become in-phase with each other, with the result that the output frequency fout becomes equal to N.multidot.fr.
FIG. 2 shows the construction of the conventional phase detector 1. The phase detector 1 is made up of a phase difference signal generator 10 and a phase difference detector 14. The phase difference signal generator 10 includes two D flip-flops 11 and 12 and a NAND gate 13. The two signals fv and fr to be compared in phase are applied to clock input terminals CK of the D flip-flops 11 and 12, respectively. A voltage VCC of an H-logic level is applied to a date input terminal D of each of the D flip-flops 11 and 12.
Phase difference signals .phi.v and .phi.r from output terminals Q of the D flip-flops 11 and 12 are applied to two inputs of the NAND gate 13, the output of which is fed to clear terminals CLR of the D flip-flops 11 and 12. Consequently, when the output terminals Q of the D flip-flops 11 and 12 both go to H-logic, the D flip-flops 11 and 12 are cleared and the output terminals Q both return to the L-logic state.
In this way, there can be obtained at the output terminals Q of the D flip-flops 11 and 12 the two phase difference signals .phi.v and .phi.r which rise at a time interval corresponding to the phase difference .phi. between the two input signals fv and fr but simultaneously fall as depicted in FIG. 3. The phase difference signals .phi.v and .phi.r are provided to the phase difference detector 14. The phase difference detector 14 detects the difference in rise time between the phase difference signals .phi.v and .phi.r and outputs the difference after subjecting it to low-pass filtering. Thus it is possible to obtain a voltage Vout corresponding to the phase difference .phi. between the two input signals fv and fr.
With the construction of the phase detector 1 shown in FIG. 2, as the phase difference between the two input signals fv and fr approaches zero, the pulse widths of the phase difference signals .phi.v and .phi.r provided from the output terminals of the D flip-flops 11 and 12 become very narrow as depicted at the right-hand side in FIG. 3, resulting in the peak values of the phase difference signals .phi.v and .phi.r becoming unstable. In order words, the peak values of the phase difference signals .phi.v and .phi.r gradually diminish as the phase difference .phi. is reduced toward zero.
As the result of this, when the phase difference is close to zero, the output voltage of the phase difference signal generator 10 becomes extremely low and its sensitivity also lowers accordingly. In consequence, the phase difference .phi. between the two signals fv and fr and the output voltage Vout bear a relationship which is nonlinear in the vicinity of the phase difference .phi. equal to zero as depicted in FIG. 4, and the gain of the phase detector 1 is reduced accordingly. That is to say, the phase detector 1 has a dead zone .DELTA.D in the vicinity of the phase difference .phi. equal to zero, and hence is defective in that the output frequency fout of the phase-looked loop varies in the range of the dead zone .DELTA.D.